74f1071 ?18-bit undershoot/overshoot clamp and esd protection device ?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 ja n uary 2008 74f1071 18-bit undershoot/overshoot clamp and esd protection device features 18-bit array structure in 20-pin package fast ? bipolar voltage clamping action dual center pin grounds for min inductance robust design for esd protection low input capacitance optimum voltage clamping for 5v cmos/ttl applications general description the 74f1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to pro- tect more sensitive devices from electrical overstress due to electrostatic discharge (esd). the inputs of the device aggressively clamp voltage excursions nominally at 0.5v below and 7v above ground. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. all packages are lead free per jedec: j-std-020b standard. connection diagram note: simplified component representation order number package number package description 74f1071sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74f1071msa msa20 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74f1071mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 2 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. notes: 1. voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded. 2. esd rating for direct contact discharge using esd simulation tester. higher rating may be realized in the actual application. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating t stg storage temperature ?5? to +150? t a ambient temperature under bias ?5? to +125? t j j unction temperature under bias ?5? to +150? v i input voltage (1) ?.5v to +6v i i input current (1) ?00ma to +50ma esd (2) human body model (mil-std-883d method 3015.7) iec 801-2 machine model (eiajic-121-1981) ?0kv ?kv ?kv dc latchup source current (jedec method 17) ?00ma pa c kage power dissipation @ +70? soic package 800mw symbol parameter rating t a f ree air ambient temperature 0? to +70? v z reverse bias voltage 0v to 5.25 v dc ja thermal resistance (in free air) soic package ssop package 100?/w 110?/w
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 3 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device dc electrical characteristics symbol parameter conditions t a = +25? t a = 0? to +70? units min. typ. max. min. max. i ih input high current v in = 5.25v; untested input @ gnd 1.5 10 50 ? v in = 5.5v; untested input @ gnd 320 100 v z reverse voltage i z = 1ma; untested inputs @ gnd 6.6 6.9 7.2 5.9 7.7 v i z = 50ma; untested inputs @ gnd 7.1 7.5 8.0 v f f orward voltage i f = ?8ma; untested inputs @ 5v ?.3 ?.6 ?.9 ?.3 ?.9 v i f = ?00ma; untested inputs @ 5v ?.5 ?.1 ?.5 ?.5 ?.5 i ct adjacent input crosstalk 3% c in input capacitance (small signal @ 1mhz) v bias = 0 v dc 25 pf v bias = 5 v dc 13
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 4 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device dc electrical characteristics typical forward and reverse v/i characteristics typical reverse conduction characteristics typical forward conduction characteristics esd network cz rz human body model 100pf 1500 ? iec 801-2 150pf 330 ? simulated esd voltage clamping test circuit
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 5 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device dc electrical characteristics (continued) unclamped +1kv esd voltage waveform (iec801-2 network) unclamped -1kv esd voltage waveform (iec801-2 network) clamped +1kv esd voltage waveform (iec801-2 network) c lamped -1kv esd voltage waveform (iec801-2 network) t ypical application 74f1071 esd protection of asic on user port
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 6 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device physical dimensions figure 1. 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 0.10 c c a see detail a notes: unless otherwise specified a) this package conforms to jedec ms-013, variation ac, issue e b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. e) landpattern standard: soic127p1030x265-20l pin one indicator 0.25 1 10 b c a m 20 11 b x45 8 0 seating plane gage plane detail a scale: 2:1 seating plane land pattern recommendation f) drawing filename: mkt-m20brev3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 max 0.30 0.10 0.33 0.20 0.75 0.25 (r0.10) (r0.10) 1.27 0.40 (1.40) 0.25 d) conforms to asme y14.5m-1994
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 7 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device physical dimensions (continued) figure 2. 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 8 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device physical dimensions (continued) figure 3. 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?994 fairchild semiconductor corporation www.fairchildsemi.com 74f1071 rev. 1.4.0 9 trademarks th ef ollowing includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global s ubsidiaries, and is not intended to be an exhaustive list of all such trademarks. acex build it now coreplus crossvolt ctl current transfer logic ecospark ezswit ch * fairchild fairchild semiconductor fact quiet series fact fast fastvcore flashwriter ? fps frfet global power resource sm green fps green fps e-series gto i-lo intellimax isoplanar m egabuck mi crocoupler microfet micropak mi llerdrive mo ti on-spm optologic optopl anar pdp-spm pow er220 pow er247 poweredge power-spm po we rtrench pr ogrammable active droop qfet qs qt optoelectronics quiet series rapidconfigure smart start spm stealth s uperfet su persot -3 s upersot -6 s upersot -8 syncfet the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinypwm tinywire serdes uhc ultra f rfet unifet vcx *ezswi tch and flashwriter are trademarks of system general corporation, used under license by fairchild semiconductor. disc laimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any pro duct or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these speci fications do not expand t he terms of fairchild? wo rl dw ide terms and conditions, specifically the warranty therein, which covers these products. life support policy fa i rchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ic h, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pr oduct status definitions defi nition of terms da tasheet identification product status definition ad vance information form first production ative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to ma ke c hanges at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the des i gn. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i32 74f1071 ?18-bit undershoot/overshoot clamp and esd protection device
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